Model checking has become a critical technique in the EDA industry. Since the early days of model checking, the algorithms have improved a lot and are now able to handle substantial hardware designs. Today, various complementary verification techniques are available, including binary decision diagrams (BDDs), SAT-based bounded model checking (BMC), interpolation, and Aaron Bradley’s IC3.
Temporal logics, like LTL, CTL, and CTL*, have proven to be flexible specification languages for various application areas and their verification is well understood. However, a class of system properties with ever growing importance turned our to be inherently not expressible in standard temporal logics. One example are properties that specify how information spreads (flows) in a system, so called information-flow properties. Information-flow is typically specified as the comparison of multiple executions of the system.
Recent extensions to temporal logics alleviate this shortcoming. HyperLTL and HyperCTL* introduce quantifiers that extend the quantification of CTL* by path variables. MCHyper is a model checker for the alternation-free fragments of HyperLTL and HyperCTL* that builds on the standard verification techniques from hardware model checking. Thereby, MCHyper enables the verification of hardware designs for intricate information-flow properties. HyperLTL and HyperCTL* also include properties from other application domains. The case studies that are provided with this tool include the analysis of symmetries among the processes in a mutual exclusion protocol, and the distance of code words of error resistant codes.